1. Field of the Invention
The present disclosure generally relates to the process of depositing a material on a substrate using a position-dependent controllable deposition tool, and, more particularly, to automatic deposition profile targeting for depositing copper to a predetermined deposition profile.
2. Description of the Related Art
The demand for higher integration, higher clock frequencies and smaller power consumption in microprocessor technology leads to a new chip interconnection technology, using copper instead of aluminum for chip wiring. Since copper is a better conductor than aluminum, chips using this technology may have smaller metal components and use less energy to pass electricity through them. These effects lead to a high performance of the integrated circuits.
The transition from aluminum to copper, however, required significant developments in fabrication techniques. Since volatile copper compounds do not exist, copper cannot be patterned by photoresist masking and plasma etching, such that a new technology for patterning copper had to be developed, which is known as a copper damascene process. In this process, the underlying silicon oxide insulating layer is patterned with open trenches where the conductor should be filled in. A thick coating of copper that significantly overfills the trenches is deposited on the insulator and chemical mechanical planarization (CMP), also known as chemical mechanical polishing, is used to remove the copper to the top level of the trench.
Since copper may not be deposited efficiently by physical vapor deposition, for example, by sputter deposition, with a layer thickness on the order of 1 μm and more, electroplating of copper and copper alloys is the currently preferred deposition method of forming metallization layers. Although electroplating of copper is a well-established technique, reliably depositing copper over large diameter substrates, having a patterned surface including trenches and wires, is a challenging task for process engineers. At a first glance, it appears to be advantageous that the metal thickness profile across the substrate surface may be formed as uniformly as possible. However, post-plating processes may require a differently shaped profile so as to assure proper device functionality of the completed integrated circuits. Currently, there is no effective copper dry etching method because of problems removing low volatility copper compounds. Presently, chemical mechanical polishing (CMP) is used for removing excess copper. Since the CMP process is per se a highly complex process frequently exhibiting an intrinsic process non-uniformity, i.e., a non-uniform removal rate across the substrate surface, it may be preferable to adapt the metal thickness profile to the post-plating process to achieve in total an improved process uniformity after the completion of the post-plating process. Therefore, electroplating tools are often configured so as to allow a variation of the metal profile, for instance by using multiple anodes on an ECD (electrochemical deposition) copper plating tool.
All current systems were using unpatterned test wafers to adjust the plating profile. FIG. 1 illustrates an adjustment scheme for adjusting a plating profile. In FIG. 1, an unpatterned test wafer 1 is coated in a plating tool 2 with copper. A four-point-probe 3 measures a copper profile of the unpatterned coated wafer. A controller 4 compares the measured data with a profile target and calculates corrections if the measured copper profile does not match with the profile target. The controller 4 then updates the tool settings of the plating tool 2. The profile target inputted to the controller 4 considers chemical mechanical polishing characteristics of the chemical mechanical polishing (CMP) tool. The plating tool 2 is an electroplating system having a plurality of individually drivable anode portions, thereby defining a multiple anode configuration. A substrate holder may be configured as a cathode and, by individually adjusting each anode current, a plating profile across a substrate surface may be controlled. The tool settings are adjusted in repetitively running test wafers as long as the difference between the profile target and the measured profile falls below a predetermined value.
Once appropriate tool settings have been found, a patterned product wafer may be plated with copper. This is exemplified in FIG. 2. Copper is electrochemically deposited with the plating tool 2 onto a patterned product wafer 5. The plating tool settings for base shaping of the deposition profile for compensating chamber characteristics is done by qualification of unpatterned test wafers as described in connection with FIG. 1. Constant offsets are applied to these settings in order to take into consideration profile deviations due to the patterns on the product wafer. In case of a multi-anode plating tool, a constant offset is applied to each of the anodes of the plating tool.
After plating the patterned product wafer, it is treated with chemical mechanical polishing 6 in order to finish the copper wirings. By polish endpoint tracing 7, or other adequate measurements, for instance, motor current control, post polish thickness or sheet resistance measurements, chemical mechanical polishing 6 parameters may be adjusted to appropriately remove excess copper. Since the plating tool settings are fixed once appropriate settings have been found, this method is designated as a static method.
It has to be noted that the characterization of the process illustrated in FIG. 2 needs to be done individually per layer and product if there are significant differences in percentages of open areas, die sizes and wafer stepping. All these efforts lead to a consumption of a certain amount of wafers to find the right shaping, which adds cost and cycle time. The CMP process is very consumable-dependent. Therefore, a one-time snap shot is not always relevant for the whole population of product wafers. Additionally, there is an individual operator and/or engineering dependence. A further drawback of the static method is that process fluctuations cannot be compensated for. For instance, the electrolyte concentration may change with time which leads to a change of the plating profile. Anodes or cathodes may corrode with time such that the plating settings become inadequate. Chemical mechanical polishing conditions may change due to deterioration of the tool characteristics. As a consequence, additional qualification runs of unpatterned test wafers have to be carried out in order to re-adjust the tool settings, i.e., the plating tool and the CMP tool.
FIG. 3 exemplifies some of these drawbacks. FIG. 3a (left hand upper part) shows an unpatterned test wafer 1 which has been coated with copper in a chamber with tool A such that its deposition profile matches with the target profile. FIG. 3b (right hand upper part) shows the same with a different tool B. FIG. 3c (left hand lower part) shows a patterned product wafer 5 which has been coated with copper in chamber tool A using the same settings as in FIG. 3a. As can be seen in FIG. 3c, the thickness profile is different as shown in FIG. 3a due to a chamber offset and the patterns on the product wafer 5. Chamber offset means that the product wafer is not coated immediately after a test wafer run such that plating conditions like consumable status and chamber status due to aging may have changed. Also the patterns on the product wafer, like trenches and their width and depth, may influence the electrical field that is necessary for the plating process. FIG. 3d (right hand lower part) shows another product wafer 5 which has been coated in chamber tool B with copper. Even if the patterns on the product wafer are the same as in FIG. 3c, and even if the profile of a test wafer is the same in chamber tool B and chamber tool A, the profile on the product wafer is different in FIGS. 3d and 3c due to plater and chamber offsets and wafer patterns.
In view of the global market forces to offer high quality products at low prices, it is thus important to improve yield and process efficiency to minimize production costs. In manufacturing modern integrated circuits, 500 or more individual processes may be necessary to complete the integrated circuit, wherein failure in a single process step may result in a loss of the complete integrated circuit. It is therefore crucial for manufacturing integrated circuits that each individual step reliably has the desired result, thereby requiring as little as possible resources.
The present disclosure is directed to various methods and systems that may avoid, or at least reduce, the effects of one or more of the problems identified above.